SoC Front-End Design Manager

Our client, a Singapore-based IC design house specializing in MCU, BMS, BLE, and TPM chip solutions for consumer electronics, automotive, industrial, and IoT applications, is seeking a qualified candidate to join their team as:

SoC Front-End Design Manager

Scope

Lead a front-end design team of 8-10 engineers as both design lead and people manager, owning microarchitecture definition and RTL implementation across our IC portfolio, partnering closely with architecture, verification, and back-end teams to hit functional, performance, power, and area targets.

Responsibilities

• Lead the front-end design team's planning and execution, setting technical direction aligned with project schedules

• Mentor and develop design engineers on RTL, microarchitecture, and CDC practices, supporting their career growth

• Drive microarchitecture definition and design trade-offs from system architecture down to block-level implementation

• Develop and review design specifications, ensuring they are clear and traceable for downstream teams

• Drive synthesis, timing closure, and DFT integration with back-end and physical design teams

• Partner with architecture, verification, and back-end teams to resolve design issues through tape-out

• Conduct design and code reviews, ensuring RTL coding standards, low-power techniques, and IP reuse best practices

• Improve front-end design methodologies, flows, and EDA tooling to boost productivity

• Stay current on emerging microarchitecture techniques and AI-assisted design methods

Requirements

• Bachelor's, Master's, or PhD in EE, CE, or related field

• 8+ years in front-end IC design with strong RTL/microarchitecture experience; 3+ years in a management or technical design-lead role

• Deep knowledge of digital logic, computer architecture, and microarchitecture — including pipelining, bus protocols, and clocking/reset design

• Proficient in RTL design (Verilog/SystemVerilog), synthesis (Design Compiler, Genus), and STA fundamentals

• Skilled in low-power design techniques (UPF, clock/power gating) across multiple power domains

• Knowledge of DFT principles (scan insertion, JTAG/boundary-scan)

• Knowledge of CDC analysis and synchronization techniques, including sign-off methodology

Preferred

• Full front-end design cycle experience, architecture through tape-out handoff

• Hands-on experience architecting complex IP (FIFOs, bus interconnects, memory controllers, clock/reset units)

• Experience managing teams of 10+ engineers across multiple concurrent projects

EA Personnel Registration No: R1106329

EA License No: 12C6254